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Synopsys Library Compiler (LC) vW-2024.09-SP1 - Nyomtatható verzió +- HHWForum.hu (https://hhwforum.hu) +-- Fórum: Letöltések (https://hhwforum.hu/forum-9.html) +--- Fórum: Programok (https://hhwforum.hu/forum-49.html) +--- Téma: Synopsys Library Compiler (LC) vW-2024.09-SP1 (/thread-484603.html) |
Synopsys Library Compiler (LC) vW-2024.09-SP1 - OS9999 - 2026-08-27 ![]() Free Download Free Download Synopsys Library Compiler (LC) vW-2024.09-SP1 | 1.7 Gb Synopsys Library Compiler (LC) is an electronic design automation (EDA) utility for processing ASIC technology libraries. It parses library information and converts it into Synopsys internal database format for physical synthesis or VHDL format for simulation. The software is intended for semiconductor design workflows where technology libraries contain functional, timing, area, and other cell-related information. By validating and translating this textual library data, Library Compiler provides formats that can be used across Synopsys design applications. Software Overview Library Compiler processes ASIC technology library files containing descriptions of logic cells and their associated characteristics. These libraries can include functional descriptions as well as timing, area, and other information required during semiconductor design and implementation. The tool parses textual library information to check its completeness and correctness before converting the data into a Synopsys internal database format. This database format can then be used by Synopsys applications for physical synthesis. The software can also translate library information into VHDL format for simulation workflows. Library Compiler is operated through the lc_shell command in a UNIX shell environment. Its capabilities can also be used from within dc_shell, allowing library processing functionality to be incorporated into related Synopsys design workflows. Key Features
Synopsys Library Compiler (LC) is designed for semiconductor workflows that require technology library information to be validated and converted into formats used by Synopsys design tools. Its library-processing capabilities help prepare ASIC cell data for physical synthesis and simulation. The ability to work with Synopsys internal database and VHDL formats also makes the tool suitable for workflows where library data must be shared between different stages or tools in an EDA environment. System Requirements
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